1. Field of the Invention
The present invention relates to a memory array cell reading circuit.
2. Discussion of the Related Art
As is known, in currently marketed nonvolatile memories, the array cells are read by comparing the content of the cells with the known content of a selected reference cell. More specifically, the cell to be read (together with other cells in the same column of the array) is connected to an array bit line, while the reference cell (normally a virgin or erased cell) is connected (possibly with other reference cells in the same column) to a reference line. Via a respective decoding circuit, the bit lines are connected to a current/voltage converter (hereinafter also referred to as an array converter) which in turn is connected to the supply.
The decoding circuit (controlled by a decoding signal) provides for read-enabling a specific bit line by connecting it to the respective array converter. The array converter comprises a precharge circuit and a load connected in series, the node between which constitutes the output of the array converter and is connected to one input of a sense amplifier, another input of which is connected to the output of a reference current/voltage converter (hereinafter also referred to as a reference converter) located between the reference line and supply and presenting the same structure as the array converter.
According to one known solution, the reference converter is the same as that of the array converter, except for the load which is doubled. Additionally, the reference and array converter loads are current mirror connected so that the current supplied to the cell to be read is half that of the current supplied to the reference cell.
Reading consists of (1) a first precharging and equalizing step wherein the selected bit line (connected to the cell to be read) and the reference line are biased to a predetermined voltage, and the cell to be read and the reference cell are appropriately biased at the control terminal; and (2) a detecting step wherein the output of the sense amplifier is read.
In the equalizing step, the output voltage of the reference converter initially falls from the supply value to an intermediate reference value; whereas the output voltage of the array converters initially falls from the supply value to a low value. If the cell to be read is erased, the output voltage subsequently settles at a low value, below the reference value, due to the cell receiving less than the required current (i.e., since the current supplied to the cell to be read is half that of the reference cell). Conversely, if the cell to be read is written, it absorbs almost no current, and the output node switches to a high voltage approximating the supply voltage. The output voltage of the sense amplifier is therefore higher than the reference voltage in the case of a written cell, and is lower than the reference voltage in the case of an erased cell, thus permitting the sense amplifier to distinguish between a written and erased cell once the output voltages of the array and reference converters settle.
In the above circuit, though essential for distinguishing between written and erased cells, the relationship between the reference and array currents is disadvantageous with regard to reading speed. In the case of a written cell, the speed at which the output voltage of the array converter switches to a high voltage after initially falling to a low value from the supply value depends on the amount of current supplied to the cell being read (i.e., the array current). Since the array current is equal to half the reference current, the above known circuit is therefore slow and involves a certain time lapse for the output voltage of the sense amplifier to reach the correct value which enables reading of the cell. What is more, due to the slowness of the circuit, the speed with which the output voltage increases may be so slow as to prevent the reading of a partially programmed (i.e., written) cell within the allotted time for reading the cell, with the result that the cell, though not actually defective and otherwise usable under enhanced speed conditions, must be rejected or redounded.